Altera Becons: Dev Series Part 1

I have started some work on my Altera MaxII Mini CPLD Kit and would be the beginning of my foray into the world of PLD. Its a refreshing experience since you are back to your Digital Logic basics that you studied in Engineering. Here is a picture of my wonderful kit.

This kit is available from Terasic and costs $69.
For Total cost to Bharath(India) Rs.1800(Shipment) + Rs.3450(Kit Cost) + Rs1490(Customs) = Rs6740/-
Thats good for the Dev Kit since its packed with lots of features and comes with the Altera QuartusII 7.2 DVD containing the essential WebPack software. The following are the Features of the Kit that make it ideal to start with:

  • On board with MAX II EPM2210F324C3 (largest CPLD in MAX II series)
  • On-board USB Blaster for Loading the CPLD and can be used as
    Stand-Alone Altera USB Blaster Cable for programming other devices
  • 4-Push button Inputs Switches with Schmitt Trigger Filter for Glitch reduction and Debouncing
  • 8-Different Color Ultra Bright LED (Active Low Interface PIN|–/\/\/\/\–|<|–|+3.3V)
  • General Purpose breakout to more than 50pins of the CPLD with Power Supply of +5V and +3.3V
  • CPLD Clock Runs at 50MHz (Way too HOT and good performance)
  • This kit can be easily interfaced to big LCD panel can be used to evaluate Graphics Driver capability.

So all the above justifies this to be a right investment I hope.

FPGA Guru:

I have done some initial work trying to use the kit and make some simple Logic Stimulus. For this I have teamed up with one of the FPGA Gurus : Mr. Jack Gassett.
He helped me by introducing me to the world of FPGA based logic Design. Also helped me identify book to help me write synthesize-able code in VHDL. I have started working with him to help make a FPGA wiki for beginners like me.

First Program on the MAXII CPLD:

For the First Post in this series I plan to show the basic code that I have written for the CPLD to behave as a not gate in VHDL. This was an attempt write the first synthesize-able code.

Listed Below is the File: Gate1.VHD
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

PORT( A : IN std_logic;
Y : OUT std_logic );

ARCHITECTURE gate1_arc OF gate1 IS
Y <= NOT A after 200 nS;

Listed below is the Main Module : Test0.VHD which actually interfaces to the CPLD pins

— Altera MAX® II EPM2210F324C3N FPGA device

— Mapping of IO for Terasic Kit [Altera MMK]

— Signal   FPGA     Description
— Name     Pin No.
— ——- ——  ——————
— LED[0]   PIN_U13  Blue LED
— LED[1]   PIN_V13  Green LED
— LED[2]   PIN_U12  Yellow LED
— LED[3]   PIN_V12  Red LED
— LED[4]   PIN_V5   Blue LED
— LED[5]   PIN_U5   Green LED
— LED[6]   PIN_V4   Yellow LED
— LED[7]   PIN_U4   Red LED
— KEY[0]   PIN_U15  Button1
— KEY[1]   PIN_V15  Button2
— KEY[2]   PIN_U14  Button3
— KEY[3]   PIN_V14  Button4
— CLOCK_50 PIN_J6   50 MHz clock input

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

    PORT( input : IN std_logic_vector(3 DOWNTO 0);
          output: OUT std_logic_vector(7 DOWNTO 0);
          clock_50M : IN std_logic );

    COMPONENT gate1
    PORT( A : IN std_logic;
          Y : OUT std_logic );
    SIGNAL led,nled :std_logic;
    PORT MAP(input(0),nled);
    led<=NOT nled;– since Leds are active Low PIN|–/\/\/\–|<|—|+3.3V

The CPLD pins are mapped as given in the comments. 
I have used all the available resources (just on board ), so that I can create a small framework to test my other code. I will try to make my Package of complete Combination Logic to work on this.  And then would be turn of the Sequential Logic.

Altera Design Contest 2009:
This might be late but I found one of the nice Design Contest for FPGA designs from Altera. Here they are even giving away the DE1 board. I would have been lucky if I would have started on this quest earlier. But, as they say – Better Luck Next time 😉


About boseji

Bharteya Anusandhankarta ( Indian Researcher)
This entry was posted in ALTERA, CPLD, FPGA, VHDL. Bookmark the permalink.

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